12小時(shí)數(shù)字鐘設(shè)計(jì)VHDL代碼Quartus仿真

名稱：12小時(shí)數(shù)字鐘設(shè)計(jì)VHDL代碼Quartus仿真

軟件：Quartus

語言：VHDL

代碼功能：

(1)輸入信號(hào)3178kh基時(shí)鐘信號(hào)。

(2)具有時(shí)、分、秒計(jì)時(shí)顯示功能,以-12小時(shí)循環(huán)計(jì)時(shí)。

(3)采用6位七段掃描共陰極數(shù)碼顯示管計(jì)時(shí)顯示,并具有秒閃指示功能。

(4)利用一個(gè)按鍵開關(guān)完成系統(tǒng)復(fù)位功能。

FPGA代碼Verilog/VHDL代碼資源下載：www.hdlcode.com

演示視頻：

設(shè)計(jì)文檔：

1. 功能描述

輸入為32.768KHz的基準(zhǔn)時(shí)鐘；

具有時(shí)分秒計(jì)時(shí)顯示功能，以12小時(shí)循環(huán)計(jì)時(shí)；

采用6位七段數(shù)碼管顯示計(jì)時(shí)；

利用一個(gè)按鍵開關(guān)完成系統(tǒng)復(fù)位功能。

2. 工程文件

3. 程序文件

4. 程序編譯

5. RTL圖

6. 仿真圖

整體仿真圖

分頻模塊

計(jì)時(shí)模塊

顯示模塊

部分代碼展示:

LIBRARY?ieee;
???USE?ieee.std_logic_1164.all;
--數(shù)字鐘
ENTITY?Digital_clock?IS
???PORT?(
??????clk_in????:?IN?STD_LOGIC;--時(shí)鐘輸入
reset????:?IN?STD_LOGIC;--復(fù)位
??????bit_select?????:?OUT?STD_LOGIC_VECTOR(5?DOWNTO?0);--數(shù)碼管位選
??????seg_select?????:?OUT?STD_LOGIC_VECTOR(7?DOWNTO?0)--數(shù)碼管段選
???);
END?Digital_clock;
ARCHITECTURE?trans?OF?Digital_clock?IS
--模塊聲明
???COMPONENT?display?IS
??????PORT?(
?????????clk????????:?IN?STD_LOGIC;
?????????hour_time??:?IN?STD_LOGIC_VECTOR(7?DOWNTO?0);
?????????minute_time?:?IN?STD_LOGIC_VECTOR(7?DOWNTO?0);
?????????second_time?:?IN?STD_LOGIC_VECTOR(7?DOWNTO?0);
bit_select?????:?OUT?STD_LOGIC_VECTOR(5?DOWNTO?0);--數(shù)碼管位選
seg_select?????:?OUT?STD_LOGIC_VECTOR(7?DOWNTO?0)--數(shù)碼管段選
??????);
???END?COMPONENT;
???
???COMPONENT?fenping?IS
??????PORT?(
?????????clk_in????:?IN?STD_LOGIC;
?????????clk_1Hz????:?OUT?STD_LOGIC
??????);
???END?COMPONENT;
???
???COMPONENT?jishi?IS
??????PORT?(
?????????clk_in????:?IN?STD_LOGIC;
reset????:?IN?STD_LOGIC;--復(fù)位
?????????clk_1Hz????:?IN?STD_LOGIC;
?????????hour_time??:?OUT?STD_LOGIC_VECTOR(7?DOWNTO?0);
?????????minute_time?:?OUT?STD_LOGIC_VECTOR(7?DOWNTO?0);
?????????second_time?:?OUT?STD_LOGIC_VECTOR(7?DOWNTO?0)
??????);
???END?COMPONENT;
???
???SIGNAL?hour_time?????????:?STD_LOGIC_VECTOR(7?DOWNTO?0);
???SIGNAL?minute_time???????:?STD_LOGIC_VECTOR(7?DOWNTO?0);
???SIGNAL?second_time???????:?STD_LOGIC_VECTOR(7?DOWNTO?0);
???
???SIGNAL?clk_1Hz???????????:?STD_LOGIC;
BEGIN
???--分頻到1Hz
???fenping_Hz?:?fenping
??????PORT?MAP?(
?????????clk_in??=>?clk_in,
?????????clk_1Hz??=>?clk_1Hz
??????);
???
???
???--計(jì)時(shí)模塊
???i_jishi?:?jishi
??????PORT?MAP?(
?????????clk_in??????=>?clk_in,
reset????=>?reset,--復(fù)位
?????????clk_1Hz??????=>?clk_1Hz,
?????????hour_time????=>?hour_time,--時(shí)
?????????minute_time??=>?minute_time,--分
?????????second_time??=>?second_time--秒
??????);
???
???--顯示模塊
???i_display?:?display
??????PORT?MAP?(
?????????clk????????????????=>?clk_in,
?????????hour_time??????????=>?hour_time,
?????????minute_time????????=>?minute_time,
?????????second_time????????=>?second_time,
bit_select?????=>bit_select,--數(shù)碼管位選
seg_select?????=>seg_select--數(shù)碼管段選
??????);
???
END?trans;

點(diǎn)擊鏈接獲取代碼文件：http://www.hdlcode.com/index.php?m=home&c=View&a=index&aid=496