2個4位計數(shù)器串聯(lián)為8位計數(shù)器VHDL代碼Quartus仿真

名稱：2個4位計數(shù)器串聯(lián)為8位計數(shù)器VHDL代碼Quartus仿真

軟件：Quartus

語言：VHDL

代碼功能：

要求

1、把兩個同步可逆計數(shù)器串聯(lián)成八位的。

2、加兩個按鍵,一個控制計數(shù)器的起始,一個控制計數(shù)器的加減。

3、最后把數(shù)字顯示在led數(shù)碼管上。

4、用 Quartus軟件vhdl語言。

5、要仿真圖。

6、盡量寫的簡單易懂。

FPGA代碼Verilog/VHDL代碼資源下載：www.hdlcode.com

演示視頻：

設(shè)計文檔：

1. 工程文件

2. 程序文件

3. 程序編譯

4. 仿真圖

部分代碼展示:

LIBRARY?ieee;
???USE?ieee.std_logic_1164.all;
ENTITY?count_8bit?IS
???PORT?(
??????reset??:?IN?STD_LOGIC;
??????en?????:?IN?STD_LOGIC;
??????up_dn??:?IN?STD_LOGIC;
??????clk????:?IN?STD_LOGIC;
??????Q??????:?OUT?STD_LOGIC_VECTOR(7?DOWNTO?0);
??????co?????:?OUT?STD_LOGIC
???);
END?count_8bit;
ARCHITECTURE?RTL?OF?count_8bit?IS
???COMPONENT?count_4bit?IS
??????PORT?(
?????????MR?????:?IN?STD_LOGIC;
?????????load_n?:?IN?STD_LOGIC;
?????????en?????:?IN?STD_LOGIC;
?????????up_dn??:?IN?STD_LOGIC;
?????????clk????:?IN?STD_LOGIC;
?????????D??????:?IN?STD_LOGIC_VECTOR(3?DOWNTO?0);
?????????Q??????:?OUT?STD_LOGIC_VECTOR(3?DOWNTO?0);
?????????co?????:?OUT?STD_LOGIC
??????);
???END?COMPONENT;
???
???
???SIGNAL?co_clk???:?STD_LOGIC;
BEGIN
????
???i0_count_4bit?:?count_4bit
??????PORT?MAP?(
?????????MR??????=>?reset,
?????????load_n??=>?'1',
?????????en??????=>?en,
?????????up_dn???=>?up_dn,
?????????clk?????=>?clk,
?????????D???????=>?"0000",
?????????Q???????=>?Q(3?DOWNTO?0),
?????????co??????=>?co_clk
??????);
???
???
???
???i1_count_4bit?:?count_4bit
??????PORT?MAP?(
?????????MR??????=>?reset,
?????????load_n??=>?'1',
?????????en??????=>?en,
?????????up_dn???=>?up_dn,
?????????clk?????=>?co_clk,
?????????D???????=>?"0000",
?????????Q???????=>?Q(7?DOWNTO?4),
?????????co??????=>?co
??????);
???
END?RTL;

點擊鏈接獲取代碼文件：http://www.hdlcode.com/index.php?m=home&c=View&a=index&aid=512