4-10譯碼器設(shè)計(jì)VHDL代碼Quartus仿真

名稱：4-10譯碼器設(shè)計(jì)VHDL代碼Quartus仿真

軟件：Quartus

語(yǔ)言：VHDL

代碼功能：

4-10譯碼器設(shè)計(jì)

要求：參考3-8譯碼器，設(shè)計(jì)4-10譯碼器，使用VHDL語(yǔ)言描述。

FPGA代碼Verilog/VHDL代碼資源下載：www.hdlcode.com

演示視頻：

設(shè)計(jì)文檔：

1. 工程文件

2. 程序文件

3. 程序編譯

4. RTL圖（根據(jù)代碼自動(dòng)生成）

5. 仿真圖

部分代碼展示:

PROCESS?(data_in)
???BEGIN
??????CASE?data_in?IS--使用case語(yǔ)句
?????????WHEN?"0000"?=>
????????????decode_out?<=?"0000000001";
?????????WHEN?"0001"?=>
????????????decode_out?<=?"0000000010";
?????????WHEN?"0010"?=>
????????????decode_out?<=?"0000000100";
?????????WHEN?"0011"?=>
????????????decode_out?<=?"0000001000";
?????????WHEN?"0100"?=>
????????????decode_out?<=?"0000010000";
?????????WHEN?"0101"?=>
????????????decode_out?<=?"0000100000";
?????????WHEN?"0110"?=>
????????????decode_out?<=?"0001000000";
?????????WHEN?"0111"?=>
????????????decode_out?<=?"0010000000";
?????????WHEN?"1000"?=>
????????????decode_out?<=?"0100000000";
?????????WHEN?"1001"?=>
????????????decode_out?<=?"1000000000";
?????????WHEN?OTHERS?=>
????????????decode_out?<=?"0000000000";
??????END?CASE;
???END?PROCESS;

點(diǎn)擊鏈接獲取代碼文件：http://www.hdlcode.com/index.php?m=home&c=View&a=index&aid=533