四路計時器Verilog代碼Quartus仿真

名稱：四路計時器Verilog代碼Quartus仿真

軟件：Quartus

語言：Verilog

代碼功能：

在quartus用Verilog，設(shè)計一個四路計時器，用四個按鍵輸入控制計時器開始、暫停、復(fù)位，單按開始、暫停，長按復(fù)位，按鍵要有消抖電路，顯示四個用6位數(shù)碼管，四個按鍵分別控制四個數(shù)碼管，計時范圍是10us--10s。

FPGA代碼Verilog/VHDL代碼資源下載：www.hdlcode.com

設(shè)計文檔：

1. 工程文件

2. 程序文件

3. 程序編譯

4. RTL圖

4通道

單通道

5. Testbench

6. 仿真圖

整體仿真圖

分頻模塊

按鍵消抖模塊

控制模塊

顯示模塊

部分代碼展示:

//?Copyright?(C)?1991-2013?Altera?Corporation
//?Your?use?of?Altera?Corporation's?design?tools,?logic?functions?
//?and?other?software?and?tools,?and?its?AMPP?partner?logic?
//?functions,?and?any?output?files?from?any?of?the?foregoing?
//?(including?device?programming?or?simulation?files),?and?any?
//?associated?documentation?or?information?are?expressly?subject?
//?to?the?terms?and?conditions?of?the?Altera?Program?License?
//?Subscription?Agreement,?Altera?MegaCore?Function?License?
//?Agreement,?or?other?applicable?license?agreement,?including,?
//?without?limitation,?that?your?use?is?for?the?sole?purpose?of?
//?programming?logic?devices?manufactured?by?Altera?and?sold?by?
//?Altera?or?its?authorized?distributors.??Please?refer?to?the?
//?applicable?agreement?for?further?details.
//?PROGRAM"Quartus?II?64-Bit"
//?VERSION"Version?13.0.1?Build?232?06/12/2013?Service?Pack?1?SJ?Full?Version"
//?CREATED"Tue?Apr?04?21:28:29?2023"
module?timmer_one(
clk_in,
key_in,
bit_select,
seg_select
);
input?wireclk_in;
input?wirekey_in;
output?wire[5:0]?bit_select;
output?wire[7:0]?seg_select;
wireSYNTHESIZED_WIRE_0;
wireSYNTHESIZED_WIRE_1;
wire[7:0]?SYNTHESIZED_WIRE_2;
wire[7:0]?SYNTHESIZED_WIRE_3;
wire[7:0]?SYNTHESIZED_WIRE_4;
controlb2v_inst(
.clk_100Hz(SYNTHESIZED_WIRE_0),
.key_value(SYNTHESIZED_WIRE_1),
.time_ms(SYNTHESIZED_WIRE_2),
.time_s(SYNTHESIZED_WIRE_3),
.time_us(SYNTHESIZED_WIRE_4));
displayb2v_inst1(
.clk(clk_in),
.time_ms(SYNTHESIZED_WIRE_2),
.time_s(SYNTHESIZED_WIRE_3),
.time_us(SYNTHESIZED_WIRE_4),
.bit_select(bit_select),
.seg_select(seg_select));
fenpingb2v_inst2(
.clk_50M(clk_in),
.clk_100Hz(SYNTHESIZED_WIRE_0));
key_jitterb2v_inst3(
.clkin(clk_in),
.key_in(key_in),
.key_value(SYNTHESIZED_WIRE_1));
endmodule

點擊鏈接獲取代碼文件：http://www.hdlcode.com/index.php?m=home&c=View&a=index&aid=446