60進(jìn)制遞減計(jì)數(shù)器Verilog代碼vivado ego1開(kāi)發(fā)板

名稱：60進(jìn)制遞減計(jì)數(shù)器Verilog代碼vivado? ego1開(kāi)發(fā)板

軟件：vivado

語(yǔ)言：Verilog

代碼功能：

60進(jìn)制遞減計(jì)數(shù)器

使用按鍵控制倒計(jì)數(shù)，按一次減1，減到0后再回到59，數(shù)碼管顯示計(jì)數(shù)值。

FPGA代碼Verilog/VHDL代碼資源下載：www.hdlcode.com

本代碼已在ego1開(kāi)發(fā)板驗(yàn)證，ego1開(kāi)發(fā)板如下，其他開(kāi)發(fā)板可以修改管腳適配：

演示視頻：

設(shè)計(jì)文檔：

1. 工程文件

2. 程序文件

3. 管腳分配

4. 程序編譯

5. Testbench

6. 仿真圖

部分代碼展示:

`timescale?1ns?/?1ps
//////////////////////////////////////////////////////////////////////////////////
//?Company:?
//?Engineer:?
//?
//?Create?Date:?2019/10/26?22:23:26
//?Design?Name:?
//?Module?Name:?adder
//?Project?Name:?
//?Target?Devices:?
//?Tool?Versions:?
//?Description:?
//?
//?Dependencies:?
//?
//?Revision:
//?Revision?0.01?-?File?Created
//?Additional?Comments:
//?
//////////////////////////////////////////////////////////////////////////////////
module?adder(
????input?clk,//100M
????input?reset_p,//復(fù)位清零
????input?sub_key,//減鍵
????output?reg?[7:0]?seg_led,//數(shù)碼管顯示
????output?reg?[1:0]?seg_select//數(shù)碼管位選
????);
//按鍵消抖
wire?sub_key_posedge;
key_jitter?i_key_jitter(
.?clkin(clk),
.?key_in(sub_key),//輸入
.?key_posedge(sub_key_posedge)//消抖后按鍵上升沿
);
reg?[7:0]?result=8'd0;
always@(posedge?clk?or?posedge?reset_p)???
????if(reset_p)//復(fù)位
????????result<=8'd0;
????else
????????if(sub_key_posedge)//按下減鍵
????????????if(result==8'd0)
????????????????result<=8'd59;
????????????else
????????????????result<=result-8'd1;
????????else
????????????;
reg?[15:0]????s1='d0;
//數(shù)碼管掃描計(jì)數(shù)
always?@(posedge?clk)
???begin
??????if?(s1?==?16'hffff)
?????????s1?<=?16'h0000;
??????else
?????????s1?<=?s1?+?1;
???end
reg?[3:0]?num_data;?
//控制數(shù)碼管位選和要顯示得數(shù)
always?@(posedge?clk)
???case?(s1[15])
??????1'b0?:begin
?????????num_data?<=?result/10;
?????????seg_select?<=2'b10;????????????
?????????end
??????1'b1?:begin
?????????num_data?<=?result%10;
?????????seg_select?<=2'b01;????????????????
?????????end
???endcase
//控制數(shù)碼管段選???
always?@(posedge?clk)
??????case?(num_data)//顯示數(shù)字
?????????4'b0000?:
????????????seg_led?<=?8'b00111111;
?????????4'b0001?:
????????????seg_led?<=?8'b00000110;
?????????4'b0010?:
????????????seg_led?<=?8'b01011011;
?????????4'b0011?:
????????????seg_led?<=?8'b01001111;
?????????4'b0100?:
????????????seg_led?<=?8'b01100110;
?????????4'b0101?:
????????????seg_led?<=?8'b01101101;
?????????4'b0110?:
????????????seg_led?<=?8'b01111101;
?????????4'b0111?:
????????????seg_led?<=?8'b00000111;
?????????4'b1000?:
????????????seg_led?<=?8'b01111111;
?????????4'b1001?:
????????????seg_led?<=?8'b01101111;
?????????default?:
????????????seg_led?<=?8'b01111001;
??????endcase
endmodule

點(diǎn)擊鏈接獲取代碼文件：http://www.hdlcode.com/index.php?m=home&c=View&a=index&aid=468